1. Field of the Invention
This invention relates to an improved magnetic bias structure which efficiently packages a plurality of magnetic bubble domain device chips having different bias requirements.
2. Description of the Prior Art
In the conventional magnetic bubble domain memory module, the required magnetic bias field is generated by inserting permanent magnets between two parallel flat plates of soft magnetic material to form a bias structure. A single uniform magnetic field is, thus, achieved in the center of the bias structure. One example of such a prior art arrangement can be found in U.S. Pat. No. 3,711,841 issued Jan. 16, 1973. The area around the perimeter of the magnets and close to the boundary of the bias plates is highly unsuitable for magnetic bubble domain chip placement, because of the fringing field effect. Therefore, to minimize the unusable area in a bias structure and, thus, reduce the size and weight of the bubble module, it is desirable to use a single bias structure which can accommodate many different memory chips. However, there are several problems associated with a large bias structure. First, a uniform magnetic field is difficult to achieve within the structure, because of the finite permeability of the bias plates. Moreover, because only a single bias field intensity can be obtained at any one time in the conventional structure, all of the chips are required to be operated under the same bias field conditions.
With present material and device processing technology, a large inventory of chips is required in order to provide chips having a bias requirement corresponding to the particular magnetic field conditions available within the bias structure. This requirement greatly limits the tolerance in wafer and device processing, and consequently requires that a large number of chips be sorted into matched groups according to their respective biasing requirements. Therefore, the result is to undesirably necessitate the use of several bias structures per bubble module in order to accommodate a large number of chips having various bias requirements.